Method for producing a iii/v si template

ABSTRACT

A method for producing a monolithic template comprises a Si wafer with a layer of a III/V semiconductor epitaxially applied to its surface. The III/V semiconductor has a lattice constant differing by less than 10% from that of Si. The method includes epitaxially growing a layer of a III/V semiconductor on the surface of the Si wafer at a wafer temperature from 350 to 650° C., a growth rate from 0.1 to 2 μm/h, and a layer thickness from 1 to 100 nm. A layer of another III/V semiconductor, identical to or different from the previously applied III/V semiconductor, is epitaxially grown on the III/V semiconductor layer at a wafer temperature from 500 to 800° C., a growth rate from 0.1 to 10 μm/h, and a layer thickness from 10 to 150 nm.

STATEMENT OF RELATED APPLICATIONS

This application claims the benefit of U.S. Provisional PatentApplication Ser. No. 61/533,296, filed Sep. 12, 2011, entitled “Methodfor Producing a III/V SI Template”, which is incorporated in itsentirety by reference herein.

FIELD OF THE INVENTION

The invention relates to a method for producing a III/V Si template orblank, respectively, preferably on silicon substrates of up to 300 mm(diameter) and larger, to templates produced by such a method and to theuses of such templates.

BACKGROUND OF THE INVENTION AND PRIOR ART

The enormous speed of progress in the computer and microchip technology,respectively, is based on the successful miniaturization of theindividual components of an integrated circuit. An integrated circuit isbasically an electronic connection of semiconductor components andpassive components for data processing, said components being producedin a thin crystal layer at the surface of a silicon substrate. Thenumber of the integrated electronic components, such as transistors,diodes, resistors and capacitors, is very high. In order to increase theperformance of the microchips and to lower at the same time theproduction cost, the packing density of the components is significantlyincreased in every new technology generation. The most importantcomponent of an integrated circuit is the silicon-based CMOS logic withn- or p-MOS-FET transistor (complementary metal oxide semiconductor). Inparticular the physical properties of silicon and silicon dioxide haveallowed a substantial reduction of the transistor size in the lastdecades. Correspondingly, the transistor density in the microchipdevelopment could be doubled every 24 months.

Transistors are basically resistances controlled by an external gatevoltage (voltage at the control electrode). Crucial performancecharacteristics of these components are high clock rates and a low heatdissipation in operation. Up to now, these performance characteristicscould be improved by the structure reduction of the transistors. In themeantime, however, the individual component dimensions are so small thatfundamental physical limits are reached and further miniaturization willnot lead to an improvement. Meanwhile, besides silicon and silicondioxide, new materials are used at this place for producing integratedcircuits, the physical properties of said materials leading to animprovement of the component functionality.

In particular, the use of III/V semiconductor materials in the CMOStechnology is discussed. The class of the III/V semiconductor crystalsis composed of 50% each of the chemical elements of group III and groupV. The binding properties of the respective chemical elements determinethe electronic and optical properties of the III/V semiconductorcompound. Since the composition options within the class of the III/Vsemiconductor materials is very large, correspondingly very differentsemiconductor components can be achieved. The integration of III/Vsemiconductor layers on Si-based integrated circuits allows on the onehand improving existing functionalities, such as the application ofIII/V channel layers for transistors. On the other hand, novel deviceconcepts can be obtained, such as the integration of III/V laser diodesfor optical data processing on the microchip level.

Another crucial point for the application of new materials for improvingthe performance of the integrated circuits is the integration process.Herein it is important, despite novel materials and/or device concepts,to keep the production costs low. Contrary to hybrid integrationapproaches (see for instance EP 0297483), the monolithic growth of III/Vsemiconductor layers on Si substrates is a very inexpensive method.Herein, the III/V semiconductor mixed crystal is directly connected withthe silicon carrier substrate (see as examples only U.S. Pat. No.5,937,274 or PCT/DE 2006/000140).

Because of the different material class of silicon and III/Vsemiconductors, the following aspects have to be taken into account forthe monolithic connection: The atomic binding properties of silicon andof the III/V class elements are very different, consequently most III/Vcrystals have a lattice constant different from that of silicon. Thedifference of the lattice constants will in turn lead to the formationof dislocation defects during the precipitation of a III/V film on Si.Besides, an interdiffusion at the boundary between silicon and the III/Vcrystal and/or contamination effects during the crystal growth may leadto a doping in the respective host crystal that is difficult to control.

Another problem is caused by the different crystal base of Si and III/Vcrystals: If the Si surface comprises non-atomically double-layerstepped Si terraces, anti-phase defects will be formed in the III/Vfilm. Since the 80s, the monolithic integration of III/V layers onsilicon was investigated. Basically, the above challenges for the III/Vprecipitation on small Si substrates of up to 2 inch diameter aresolved, however the formation of dislocations during the integration ofIII/V materials with lattice constants different from that of siliconstill complicates the realization of highly efficient components withsufficient life.

Because of the different crystal base of silicon and III/V mixedcrystals, anti-phase defects in the III/V layer may very quickly beformed during the monolithic precipitation. These defects in turn impairthe operating properties of the components. The formation of anti-phasedefects can be avoided by the specific preparation of the siliconsurface.

An anti-phase-free III/V integration is possible, if by a specialsubstrate pretreatment double-steps of two Si atomic layers each areproduced. This surface preparation is however preferably possible onslightly dislocated [(001) 2° to 6° off in the <110> direction]substrates. In the document B. Kunert, I. Németh, S. Reinhard, K. Volz,W. Stolz, Thin Film Solid 17 (2008) 140, the defect-free precipitationof GaP on exactly oriented substrates was shown for the first time,however the substrate specification is still subject to an additionalrequirement: (001) (smaller than) <0.15° off in the <110> direction.

Since today's Si-based CMOS technology is very complex and advanced, theintegration of new materials must be matched very precisely with theCMOS production process. Any larger intervention or change of thecurrent CMOS process would significantly increase the development costs.The CMOS standard Si substrate specification with respect to theorientation is (001) +/−0.5 off in an arbitrary direction. Theconversion of the CMOS technology to dislocated [(001) 2° to 6° off inthe <110> direction] substrates would however by much too expensive anduneconomical due to the renewed adjustment of the process.

The above-mentioned substrate specification of (001) <0.15° off in the<110> direction would however fall into the specification of the CMOSprocess. However, due to this small dislocation, the specific wafersawing process is very complicated and expensive and is still a bigtechnological challenge. In the meantime, the Si substrate size in theactual CMOS technology is a diameter of 300 mm (some factories work withan even smaller wafer). The mass production of 300 mm Si wafers with adislocation of <0.15° in the <110> direction would however drasticallyincrease the production costs, and then the application of thesesubstrates would be economically questionable. Therefore, in particularthe anti-phase-free III/V integration on 300 mm Si substrates is anunsolved technological and economical problem for the CMOS process.

Another technological challenge is caused by the different thermalexpansion coefficients of silicon and the compounds of the III/Vsemiconductor crystals. When the different dependence of the latticeconstants on the temperature is not systematically taken into account inthe integration process, dislocations or cracks may be formed in theIII/V layer. For large substrate diameters, the Si wafer may even beaffected (wafer flipping) and form relaxation defects.

TECHNICAL OBJECT OF THE INVENTION

It is therefore the technical object of the invention to propose amethod for producing a monolithic III/V Si template having minimaldislocation defects, minimal anti-phase defects, and allowing the use ofcomparatively large Si wafers with diameters of 200 mm, 300 mm or largerthat optionally may have a mask structure.

BASICS OF THE INVENTION

For achieving this technical object, the invention teaches a method forproducing a monolithic template comprising a Si wafer with a layer of aIII/V semiconductor epitaxially applied on a surface of the Si wafer,the III/V semiconductor having a lattice constant, which differs by lessthan 10% from that of Si, comprising the following steps: A) optionally,the surface of the Si wafer is deoxidized, B) optionally, a Si layer isepitaxially grown on the surface of the deoxidized Si wafer, C)optionally, the surface of the Si wafer or the surface of the Si layeris subjected to a baking-out step and/or an etching step, D) a layer ofa III/V semiconductor is epitaxially grown on the surface of the Siwafer or a surface formed during one of steps A) to C) at a wafertemperature from 350 to 650° C., a growth rate from 0.1 to 2 μm/h, and alayer thickness from 1 to 100 nm, E) a layer of a III/V semiconductor,identically with or differently from the III/V semiconductor applied instep D), is epitaxially grown on the layer obtained in step D) at awafer temperature from 500 to 800° C., a growth rate from 0.1 to 10μm/h, and a layer thickness from 10 to 150 nm.

The invention thus comprises a special method of the crystallineprecipitation of group IV materials as well as III/V semiconductorcompounds on Si substrates, these Si substrates having a diameter of 200mm, 300 mm and more and optionally being structured by means of masking.The crystal precipitation or the crystal growth, respectively, typicallytakes place by means of gas phase epitaxy. With this process, theintegration of a thin dislocation-free III/V semiconductor layer on Sisubstrate is intended and ideally also achieved.

At the beginning of the process, the Si substrates can be baked out in afirst process step, in order to remove the silicon dioxide from thesurface. In the next step, a silicon buffer can be precipitated ifrequired. Depending on the integration concept, this silicon buffer canbe doped. The Si substrate surface with or without additional bufferlayer is for instance, but not necessarily specially prepared, dependingon the crystal dislocation (off or exactly oriented). The precipitationof steps D) and E) occurs in two process steps: First a thin III/V filmis grown at low temperatures (step D)) and then the reactor temperatureis significantly increased for the further crystal precipitation (stepE)). The composition of the III/V layer is adjusted, depending on layerthickness and growth temperature, in order to avoid the formation ofdislocations and cracks or reduce them as far as possible.

Contrary to most other III/V mixed crystals, the monolithic integrationof thin GaP layers on Si substrate is possible without the formation ofdislocation defects, since the two crystals have a similar latticeconstant. Thus the application of GaP as a first III/V nucleation layeris technologically very important, since this also appreciablysimplifies the further integration of materials with a different latticeconstant. This GaP/Si template can consequently be used for verydifferent III/V materials and (electronic) component concepts on Simicroelectronics. At present, various enterprises, institutes anduniversities work on specific integration concepts under application ofa GaP/Si template.

The invention allows for the first time the precipitation of practicallydislocation-free III/V semiconductor materials on exact and dislocatedsilicon substrate having a diameter of up to 300 mm. In the processdesign, it has also been taken into account that before theprecipitation of III/V materials, a silicon buffer with arbitrary dopingcan be realized. This step is particularly helpful, in order on one handto optimize the substrate surface, to permit selective siliconovergrowth in particular for a mask structuring process and toprecipitate adjusted Si contact layers for the standard CMOSmetallization. The use of 300 mm wafers corresponds to today's Si-basedCMOS technology, thus the integration method on corresponding waferspermits maximum compatibility with the current development state of theCMOS technology.

Furthermore, by the use of 300 mm substrates, an ideal costeffectiveness of the production costs is assured. In particular sincethe process has been realized in an epitaxy system that is connectedwith an automatic disc handler, and thus an automatic substrate transferis possible.

Besides the application of the invention in the Si microtechnology, theprecipitation of III/V materials on large-area Si substrates isadvantageous for other applications, too. It is the intention here tobenefit of the fact that Si substrates are significantly less expensivecompared to conventional III/V substrates, and that larger substratediscs can also be produced.

By the integration of conventional III/V-based components such as LEDs,detectors or solar cells on Si substrates, the production costs couldsignificantly be reduced. At this point, the use of dislocated ((001) 2°to 6° off in the <110> direction) Si substrates would also be possible.

In particular, the following preferred variants of the method accordingto the invention are described.

The surface to be coated of the Si wafer is preferably a (001) Sisurface, with 0 to 6°, in particular 0 to 2°, dislocation in thedirection <110>. In addition, the Si wafer may have a mask structure.For a dislocation of ≦1°, the direction of the dislocation may differfrom <110>.

Step A) can be carried out by baking-out to a wafer temperature from 800to 1,200° C., in particular 900 to 1,100° C., for instance 950 to 1,050°C., for a time from 1 s to 30 min, in particular a time from 1 to 30min, for instance 5 to 15 min, in an inert gas atmosphere. The inert gasatmosphere can be nitrogen or hydrogen. The (total) gas pressure may bein the range from 50 to 1,000 mbar, preferably 100 to 300 mbar. Thetotal gas flow may be in the range from 6 to 200 l/min, in particular 6to 50 l/min, for instance 40 to 50 l/min.

In step B) the Si layer can be grown at a wafer temperature from 600 to1,200° C., in particular from 725 to 1,100° C., for instance from 850 to1,050° C., a growth rate from 0.01 to 20 μm/h, in particular 1 to 10μm/h, for instance 3 to 10 μm/h, and a layer thickness from 0 to 5 μm,in particular 0.1 to 2 μm, for instance 0.5 to 1.5 μm. The inert gasatmosphere may be nitrogen or hydrogen under additional use of a gaseousSi educt. Optionally, a doping with B, Ga, P, Sb and/or As in a p- orn-doping concentration of 10¹⁵ to 10²¹ cm⁻³, for instance 10¹⁷ to 10²¹cm⁻³ is carried out. The (total) gas pressure may be in the range from50 to 1,000 mbar, preferably 100 to 300 mbar. The total gas flow may bein the range from 6 to 200 l/min, in particular 6 to 50 l/min, forinstance 40 to 50 l/min.

In step C), an inert gas or protective gas (for instance N₂ or Ar),respectively, or an active gas can be conducted at a wafer temperaturefrom 600 to 1,200° C., in particular 725 to 1,100° C., for instance 850to 1,050° C., for a time from 0 to 60 min, in particular 0 to 15 min,for instance 1 to 10 min, over the surface at an etching rate from 0 to5 μm/h, preferably 0 to 2 μm/h. As active gas, for instance HCl orhydrogen may be used (remainder: for instance nitrogen). The (total) gaspressure may be in the range from 50 to 1,000 mbar, preferably 600 to900 mbar. The total gas flow may be in the range from 6 to 200 l/min, inparticular 6 to 50 l/min, for instance 10 to 15 l/min.

In step D), a Ga_(x)B_(y)Al_(z)P or a GaN_(w)P_(v) semiconductor can begrown, wherein x=0-1, y=0 to 0.1 and z=0-1, or w=0-0.1 and v=1-w, inparticular x=1, y=0 and z=0, wherein the sum of x, y and z forGa_(x)B_(y)Al_(z)P is always 1. The wafer temperature may preferably bein the range from 400 to 625° C., in particular 420 to 500° C. The III/Vgrowth rate may be in the range from 0.1 to 2 μm/h, in particular 0.5 to1.5 monolayers/s, for instance 1 monolayer/s. The growth mode may becontinuous, preferably by means of flow rate modulation epitaxy (FME)and by means of atomic layer precipitation (ALD), what can also be usedfor the layers generally or specially described otherwise. The layerthickness preferably is in the range from 2 to 50 nm, in particular 2 to8 nm. The gas proportion V/III may be in the range from 5 to 200, inparticular 10 to 150, for instance 50 to 70. The (total) gas pressuremay be in the range from 50 to 1,000 mbar, preferably 50 to 500 mbar, inparticular 50 to 150 mbar. The total gas flow may be in the range from 6to 200 l/min, in particular 6 to 60 l/min, for instance 40 to 60 l/min.Optionally, a doping with Zn, Te, S, C, Mg and/or Si takes place in a p-or n-doping concentration of 10¹⁵ to 10²¹ cm⁻³, for instance 10¹⁷ to10²¹ cm⁻³. The procedure can however also be made without doping.

In step E), a Ga_(x)B_(y)Al_(z)P or a GaN_(w)P_(v) semiconductor can begrown, wherein x=0-1, y=0-0.1 and z=0-1, or w=0-0.1 and v=1-w, inparticular x=0-1, y=0-0.06 and z=0-1, wherein the sum of x, y and z forGa_(x)B_(y)Al_(z)P is always 1. The wafer temperature may preferably bein the range from 525 to 725° C., in particular 650 to 700° C. The III/Vgrowth rate may be in the range from 0.1 to 10 μm/h, in particular 0.5to 5 μm/h, for instance 2 to 2.5 μm/h. The layer thickness preferably isin the range from 30 to 100 nm, in particular 40 to 70 nm. The gasproportion V/III may be in the range from 5 to 200, in particular 10 to100, for instance 10 to 30. The (total) gas pressure may be in the rangefrom 50 to 1,000 mbar, preferably 50 to 900 mbar, in particular 50 to150 mbar. The total gas flow may be in the range from 6 to 200 l/min, inparticular 6 to 60 l/min, for instance 40 to 60 l/min. Optionally, adoping with Zn, Te, S, C, Mg and/or Si takes place in a p- or n-dopingconcentration of 10¹⁵ to 10²¹ cm⁻³, for instance 10¹⁷ to 10 ²¹ cm⁻³. Theprocedure can however also be made without doping.

The invention furthermore relates to a monolithic template, obtainableby means of a method according to the invention. It also relates to theuse of such a template for the monolithic integration of componentsbased on III/V semiconductor layers such as transistors, laser diodes,LEDs, detectors and solar cells on a Si substrate, in particular on a Sisubstrate having a diameter of more than 6 cm, preferably more than 10cm, in particular more than 20 cm. Subsequently to step E), furtherIII/V semiconductor layers can be epitaxially grown and electroniccomponents comprising III/V semiconductor can be formed.

In the following, the invention is explained in more detail by means ofnon-limiting examples representing embodiments only.

EXAMPLE 1 Employed Devices

Crystal precipitation takes place by means of gas phase epitaxy. Forthis purpose, an epitaxy system is required that allows the crystalgrowth on 300 mm (diameter) Si substrates. Furthermore, the temperaturedistribution of the susceptor can be radially varied in the method, inorder to precisely adjust the temperature profile of the Si wafer.Preferably, the CCS (Close Couple Showerhead) Crius system from Aixtronis used.

All described process steps can be carried out in a single epitaxyreactor. In order to minimize contamination effects or to adjust theintegration method to further process steps, two epitaxy reactors mayalso be used. Therein, an optional substrate transfer after process stepC) and/or D) is recommended.

EXAMPLE 2 Employed Substances or Gases, Respectively

The following educts or precursors, respectively, can be employed in theprocess:

Educts for silicon: silane, di-chlorsilane, di-silane, tri-silane,neopenta-silane, tetra-chlorosilane (SiCl₄), di-tertiary-butyl-silane(DitButSi).

Educts for gallium: tri-ethyl-gallium (TEGa), tri-methyl-gallium (TMGa),tri-tertiary-butyl-gallium.

Educts for boron: tri-ethyl-borane (TEB), tri-tertiary-butyl-borane,di-borane, borane-amine adducts such as di-methyl-aminoborane.

Educts for aluminium: tri-methyl-aluminium (TMAl),tri-tertiary-butyl-aluminium, amine adducts such asdi-methyl-aminoaluminium.

Educts for phosphorus: tertiary-butyl-phoshine (TBP), phosphine.

Educts for arsenic: tertiary-butyl-arsine (TBAs), arsine,tri-methyl-arsine (TMAs).

Educts for antimony: tri-ethyl-antimony (TESb), tri-methyl-antimony(TMSb).

Educts for doping the III/V layer: di-ethyl-tellurium (DETe),di-methyl-zinc (DMZn), di-ethyl-zinc (DEZn), ditButSi, silane,di-tertiary-butyl-sulfide, bis-cyclopentadienyl-magnesium,tetra-bromomethane.

Cl-containing educts: HCl, di-chlorsilane, SiCl₄.

Nitrogen or hydrogen is used as carrier gases.

The following educts are preferred: silane, di-silane, di-chlorosilane,HCl, TEGa, TEB, TMAl and TBP. The preferred carrier gas is hydrogen.

EXAMPLE 3 GaP on Exact Silicon (001)

As an example of execution, the precipitation of a thin GaP layer on 300mm silicon substrate is described. In this example, the Si substrate isp-doped and exact-oriented. The GaP-layer is 50 nm thick and n-doped inthe range of 3*10¹⁸ cm⁻³. The following educts are used: silane, TEGa,TBP, and DETe.

The Si wafer is transferred by means of an automated disc-transfersystem from Brooks into a CCS Crius reactor from Aixtron. Purifiedhydrogen is used as carrier gas, whereas silane, TEGa, TBP and DETe areavailable as educts for Si, Ga, P and Te.

In the first step, the native silicon dioxide is removed from thesubstrate surface in a 10-minute baking-out step (step A). The reactorpressure is 200 mbar, the total gas flow is 48 l/min, and the wafertemperature is 1,000° C.

For the precipitation of a 1 μm-thick Si buffer (step B)), the followinggrowth parameters are adjusted: reactor pressure 200 mbar, total gasflow 48 l/min, wafer temperature 900° C. Under these conditions, asilane flow of 8.9E-4 mol/min will lead to a growth rate of 4 μm/h.

After the buffer growth, the silicon surface is prepared (step C)). Forthis purpose, a HCl flow of 5.4E-3 mol/min for 5 min into the reactor iseffected. This surface treatment initiates the formation of double-layerstepped Si terraces, in order to minimize the formation of anti-phasedefects. The reactor pressure is 700 mbar and the total flow is 12l/min.

The following nucleation of the GaP-layer again necessitates theadjustment of the growth conditions: The wafer temperature in step D) isreduced to 450° C., and a reactor pressure of 100 mbar and a total gasflow of 48 l/min are adjusted. The mole flows of the III/V educts are2.52E-4 mol/min for TEGa and 1.51E-2 mol/min for TBP. In the first stepof the III/V nucleation, TBP is fed for 10 s into the reactor (TBPpreflow). Then follows the GaP growth per FME (flow rate modulationepitaxy). This means in particular that after the TBP preflow, thefollowing educt switching sequence for the reactor is repeated severaltimes: 1 s growth interruption without educts −>1 s TEGa −>1 s growthinterruption without educts −>1 s TBP. This switching loop is repeated22 times, and thereby 6 nm GaP are precipitated. The TEGa mole flow isadjusted such that in one second the wafer surface is covered with onemonolayer Ga.

In the next step (step E)), the wafer temperature is increased to 675°C. under TBP stabilization. Further, new mole flows for the educts areadjusted: 5.81E-4 mol/min for TEGa and 1.16E-2 mol/min for TBP. Thereby,the V/III proportion is reduced from 60 to 20. The gas phase proportionDETe/TEGa is adjusted such that at 675° C. an n-doping of 3*10¹⁸ cm⁻³ isachieved. A GaP layer of 44 nm is precipitated with a growth rate of 2.3μm/s. This GaP/Si template is then cooled down under TBP stabilization.

These process parameters can also be used for (001) Si wafers with adislocation of up to 2° off in the <110> direction.

EXAMPLE 4 GaP on (001) Silicon, 2° Off in the <110> Direction of the SiWafer

As an example of execution, the precipitation of a thin GaP layer on 300mm silicon substrate is described. In this example, the Si substrate isp-doped and has a dislocation of 2° off in the <110> direction. TheGaP-layer thickness is 50 nm. The following educts are employed: silane,TEGa, and TBP.

The Si wafer is transferred by means of an automated disc-transfersystem from Brooks into a CCS Crius reactor from Aixtron. Purifiedhydrogen is used as carrier gas, whereas silane, TEGa, and TBP areavailable as educts for Si, Ga, and P.

In the first step, the native silicon dioxide is removed from thesubstrate surface in a 10-minute baking-out step (step A). The reactorpressure is 200 mbar, the total gas flow is 48 l/min, and the wafertemperature is 1,050° C.

For the precipitation of a 1 μm-thick Si buffer (step B)), the followinggrowth parameters are adjusted: reactor pressure 200 mbar, total gasflow 48 l/min, wafer temperature 1,050° C. Under these conditions, asilane flow of 8.9E-4 mol/min will lead to a growth rate of 8.3 μm/h.

A step C) is not carried out in this Example, step D) immediatelyfollows.

The following nucleation of the GaP-layer again necessitates theadjustment of the growth conditions: The wafer temperature in step D) isreduced to 450° C., and a reactor pressure of 100 mbar and a total gasflow of 48 l/min are adjusted. The mole flows of the III/V educts are2.52E-4 mol/min for TEGa and 1.51E-2 mol/min for TBP. In the first stepof the III/V nucleation, TBP is fed for 10 s into the reactor (TBPpreflow). Then follows the GaP growth per FME (flow rate modulationepitaxy). This means in particular that after the TBP preflow, thefollowing educt switching sequence for the reactor is repeated severaltimes: 1 s growth interruption without educts −>1 s TEGa −>1 s growthinterruption without educts −>1 s TBP. This switching loop is repeated22 times, and thereby 6 nm GaP are precipitated. The TEGa mole flow isadjusted such that in one second the wafer surface is covered with onemonolayer Ga.

In the next step (step E)), the wafer temperature is increased to 675°C. under TBP stabilization. Further, new mole flows for the educts areadjusted: 5.81E-4 mol/min for TEGa and 1.16E-2 mol/min for TBP. Thereby,the V/III proportion is reduced from 60 to 20. A GaP layer of 44 nm isprecipitated with a growth rate of 2.3 μm/s. This GaP/Si template isthen cooled down under TBP stabilization.

These process parameters can also be used for (001) Si wafers with adislocation of up to 6° off in the <110> direction.

1. A method for producing a monolithic template comprising a Si waferwith a layer of a III/V semiconductor epitaxially applied on a surfaceof the Si wafer, the III/V semiconductor having a lattice constant,which differs by less than 10% from that of Si, comprising the followingsteps: A) epitaxially growing a layer of a first III/V semiconductor onthe surface of the Si wafer at a wafer temperature from 350 to 650° C.,a growth rate from 0.1 to 2 μm/h, and a layer thickness from 1 to 100nm, B) epitaxially growing a layer of a second III/V semiconductor,identical to or different from the first III/V semiconductor on thefirst III/V semiconductor layer at a wafer temperature from 500 to 800°C., a growth rate from 0.1 to 10 μm/h, and a layer thickness from 10 to150 nm.
 2. The method according to claim 1, wherein the surface of theSi wafer is a (001) Si surface, with 0 to 6° in the direction <110>,wherein at a dislocation of ≦1° the direction of the dislocation candiffer from <110>.
 3. The method according to claim 11, wherein step C)is carried out by baking-out to a wafer temperature from 800 to 1,200°C. for a time from 1 s to 30 min in an inert gas atmosphere.
 4. Themethod according to claim 11, wherein in step D) the Si layer is grownat a wafer temperature from 600 to 1,200° C., a growth rate from 0.01 to20 μm/h, and a layer thickness from 0 to 5 μm.
 5. The method accordingto claim 11, wherein in step E) an active gas, in particular aCl-containing gas and/or hydrogen, is conducted over the surface at awafer temperature from 600 to 1,200° C. for a time from 0 to 60 min atan etching rate from 0 to 5 μm/h, and/or an inert gas is conducted overthe surface at a wafer temperature from 600 to 1,200° C. for a time from0 to 60 min.
 6. The method according to claim 1, wherein in step A) aGa_(x)B_(y)Al_(z)P or a GaN_(w)P_(v) semiconductor is grown, whereinx=0-1, y=0-0.1 and z=0-1, or w=0-0.1 and v=1-w, wherein the sum of x, yand z for Ga_(x)B_(y)Al_(z)P is always
 1. 7. The method according toclaim 1, wherein in step B) a Ga_(x)B_(y)Al_(z)P or a GaN_(w)P_(v)semiconductor is grown, wherein x=0 -1, y=0-0.1 and z=0-1, or w=0-0.1and v=1-w, wherein the sum of x, y and z for Ga_(x)B_(y)Al_(z)P isalways
 1. 8. A monolithic template formed in accordance with the methodof claim
 7. 9. (canceled)
 10. The monolithic template of claim 8,wherein subsequent to step B), further comprising epitaxially growingadditional III/V semiconductor layers to form electronic components. 11.The method of claim 1 further comprising: C) deoxidizing the surface ofthe Si wafer prior to growing the first III/V semiconductor layer; D)epitaxially growing a Si layer on the surface of the deoxidized Siwafer; and E) etching and/or baking out the surface of the Si wafer. 12.The monolithic template of claim 10 wherein the electronic componentsare selected from the group selected from transistors, laser diodes,LEDs, detectors, and solar cells.
 13. The monolithic template of claim12 wherein the electronic components are formed with a mask structurehaving a diameter of more than 6 cm.
 14. The monolithic template ofclaim 13 wherein the mask structure has a diameter of more than 10 cm.15. The monolithic template of claim 13 wherein the mask structure has adiameter of more than 20 cm.